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Resume CV Kranthi Kumar Sesham Physical PD

by kranthi-kumar-sesham





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Download Resume CV Kranthi Kumar Sesham Physical PD


OBJECTIVE KRANTHI KUMAR SESHAM [email protected] CONTACT: +91- 8800466504. To work in a professional and competent atmosphere that enables me to cope with emerging technologies, to widen the spectrum of my knowledge. PROFESSIONAL EXPERIENCE RESIDENCE ADDRESS D-303, HPCL HOUSING SOCIETY, SECTOR-PI, GREATER NOIDA UTTAR PRADESH-201308. Duration Domain Company Role Manager July 2011 to Present Physical Design STMicroelectronics, Noida Graduate Intern Pankaj Panjwani PERMANENT ADDRESS: D.NO: 8-11-43/2 KOTHA BAVI BAZAR, NARASARAOPET , GUNTUR(DIST) ANDHRA PRADESH- 522601 TECHNICAL SKILL SET Backend Tools Languages OS Exposure Interest Areas Other Tools : Cadence SoC Encounter, Mentor graphics Olympus SoC : Strong Knowledge in Perl, Shell, Tcl, Vim & C : Well Versed with Unix, Linux & Windows : ASIC, Custom Design, Digital Design : Mat lab, Kiel uVision IDE, MS OFFICE. PERSONAL PROFILE: FATHER NAME: Siva Brahmam DATE OF BIRTH: 12th Aug, 1988 GENDER: Male MARITAL STATUS : Single NATIONALITY : Indian LANGUAGES : English, Hindi, Telugu SOFT SKILL SET • • • • • Self-starter and a fast learner Strong analytical and reasoning skills Capable of working as an individual or in a team Smart working nature & Good logical thinking Effective Communication ACADEMIC PROFILE • M.Tech (Digital Electronics & Advanced Communication) - 2012 CGPA(1st Year) : 7.10 Manipal Institute Of Technology, Manipal University. • • GATE - 2010 Percentile : 95.418 B.Tech (Electronics & Communication Engineering) - 2009 Percentage : 67.33 Narasaraopet Engineering College, JNT University. • Senior Secondary Education, Class XII - 2005 Percentage : 96.6 Vasavi Junior College, Narasaraopet, Andhra Pradesh. • Secondary Education, Class X - 2003 Percentage : 84.83 Sri Sarma Convents, Narasaraopet, Andhra Pradesh. PROJECT PROFILE PROJECT #1: Title: 32nm HIERARCHICAL PHYSICAL DESIGN IMPLEMENTATION AND FLOW IMPROVEMENTS Description: The project involves deep analysis and study of physical design flow and 32nm technology parameters. It will require running trials and experiments on different stages of physical design and fine tune parameters to get optimal results. A hierarchical block called clock generator is implemented using Makefile based netlist to GDSII flow. The purpose of this block is to generate high speed no jitter logical clock of 30MHZ. It contains two analog blocks (Phase Locked Loop), one digital block (registers) with some digital logic Physical description of the Clock generator block Technology 32nm Macros 99 Instances 32K Clock Domains 69 Metal Layers 10 Tools Used: Cadence SoC Encounter, Mentor Graphics Olympus SoC & ST internal tools. Over the period, the activities include 1. Setup creation 2. Floorplanning & Power Routing 3. Experimenting with different floorplans 4. Porting from 7ml to 10ml Floorplan 5. Clock tree synthesis experiments 6. Flow Kit development for place and route steps 7. Additional scripts 8. Resolving the issues occurred in the P&R flow 9. Complete Place and Route for a logic block with developed kit. 10. Participation in physical verification 11. Performed the setup creation for the same block for 28nm Script Work: POWER ATTX PARSER The power.attx format describes additional connectivity which is not explicited in the verilog netlist. Additional connectivity includes IO ring connectivity, Core power connectivity, and Tie ups/lows connectivity. The definitions of all these connectives are defined in a syntax form in this file. The script written out in perl using hash concepts & CPAN Modules, helps to parse the power attx and dumps out all the connectivity definitions into spread sheet in a readable format. Ex: Pin A of Macro B is connected to Pin C of Macro D through net name E. Net Name Macro B From (Pin) To (Pin) Macro D Type (P/G) SoC ENCOUNTER & OLYMPUS SoC REPORTS PARSER Clock tree synthesis (CTS) reports consist of summary tables of each clock with its respective parameters (skew, latency, group size, no of leaves etc.) in between the reports. It is required to parse those reports and dumped the required parameters into spreadsheet, to perform qualitative analysis between different CTS runs. This script was written in shell for both SoC Encounter & Olympus SoC tools. FLOW IMPROVEMENT SCRIPTS a. update_scripts : To update the flow kit scripts with additional needs b. update_flow_variables To update the flow scripts to set the custom variables SoC ENCOUNTER RUN LOGS REPORT GENERATOR While performing different PnR runs with changes in input files, after the execution of the run by checking logs, it’s difficult to trace out how the run get affected with extra changes in the input files as several stages (logs) have same and repetitive warnings & errors. The purpose of this script is to prepare a single RUN LOG REPORT from all the logs, which contain all unique errors and warnings and the stages where the error gets occurred. This script can also be used even for single log file as well to find out all the unique errors and warnings. In addition to the above, written out general scripts like fixing clipboard issues between VNC & Windows Machine, and other small util scripts to automize the manual tasks. PROJECT #2 Title: AUTOMATION OF APPLIANCES USING GSM Description: The main aim of this project is to control the home appliances using GSM. Any appliance is controlled by just sending a message from our mobile. The message will be read by GSM modem and which will be decoded by the microcontroller and will control respective appliance. LCD used for displaying the incoming message. Platform: Assembly Language, Keil development tool PROJECT #3 Title: STUDY REPORT ON DISTRIBUTED ARITHMETIC ALGORITHM Description: Distributed Arithmetic (DA) is basically a bit-serial computational operation that forms an inner (dot) product of a pair of vectors in a single direct step. The advantage of DA is its efficiency of mechanization. It is a good way to trade combinational logic with memory for highperformance computation. It saves gate count around 50% to 80%. Platform: Mat lab 2010 EXTRA-CURRICULAR ACTIVITIES • • • Tweaking Operating Systems, tools & playing with its features Blogging, Writing scripts to tag my music collection, E-Learning, Photography Good at playing Chess, Cricket ACHIEVEMENTS • • Stood as topper in the institution at school and college level. Participated In Several Technical Paper Contests REFERENCES • • Pankaj Panjwani - Sr. Manager at STMicroelectronics, Noida Swarnendu Mazumdar - Technical Lead at Synapse Techno Design, Bangalore (E-mail id’s provided on request) DECLARATION I declare that all the above furnished information is true and correct to the best of my knowledge and belief. Date: Place: (KRANTHI KUMAR SESHAM)
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