A Frequency Model of a Continuously Driven Clocked CMOS Comparator

  • Published on
    05-Oct-2016

  • View
    213

  • Download
    1

Transcript

956 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 57, NO. 12, DECEMBER 2010A Frequency Model of a ContinuouslyDriven Clocked CMOS ComparatorShunsuke Okura, Hajime Shibata, Member, IEEE, Tetsuro Okura,Toru Ido, Member, IEEE, and Kenji Taniguchi, Member, IEEEAbstractA frequency model of a continuously driven clockedCMOS comparator with the effect of the input signal duringregeneration is presented. The model utilizes a small-signal linearmodel derived from the theoretical analysis of the comparisonerror caused by the transition from the tracking mode to theregeneration mode. The comparison error voltage is a functionof input signal frequency and is represented with the transferfunction. The correctness of the model is assured by severaltransistor-level simulation results. The model provides a valuableinsight for the design of high-speed comparators.Index TermsClocked comparator, CMOS, frequency re-sponse, metastability, regeneration.I. INTRODUCTIONFOR THE design of analog-to-digital converters (ADCs),a comparator is a crucial and often a limiting componenttoward high-speed operation because of its finite accuracyand comparison speed. Among the main building blocks ofcomparators, flip-flops and latches have been well analyzed. Aformula describing the probability of a metastable state occur-rence has been presented in [1]. A formula for the sensitivityof a latch in a sense amplifier has been described in [2]. Thelatch has been theoretically analyzed with small-signal modelsin [3] and [4]. Moreover, there have been many reports on high-speed ADC or comparators that discuss the effect of the staticoffset voltage, the metastability, the reset time of the latch [5][10], the frequency response of the preamp [7], [11], and designoptimizations of high-speed comparators [4], [11], [12].This brief presents a frequency model of continuously drivenclocked CMOS comparators taking into account the effect ofthe input signal during regeneration. A clocked comparatorhas two modes, namely, the tracking mode and the regener-ation mode. According to the study on the transition fromthe tracking mode to the regeneration mode, the comparisonresult depends on the input signal frequency. This dependenceis caused by the input signal change just after the beginningof regeneration while the regeneration gain is still small. TheManuscript received April 19, 2010; revised July 24, 2010; acceptedOctober 11, 2010. Date of current version December 15, 2010. This workwas supported in part by a grant from the Global COE Program, Centerfor Electronic Devices Innovation, from the Ministry of Education, Culture,Sports, Science and Technology of Japan. This paper was recommended byAssociate Editor J. Paramesh.S. Okura, T. Okura, T. Ido, and K. Taniguchi are with the Graduate Schoolof Engineering, Osaka University, Suita 556-0871, Japan.H. Shibata is with Analog Devices, Inc., Toronto, ON M5G 2C8, Canada.Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TCSII.2010.2087972Fig. 1. Schematic of a clocked CMOS comparator.comparison error that depends on the input signal frequency isnamed ac error in this brief. Based on the small-signal analysis,the ac error voltage is given by a simple function of inputsignal frequency. The frequency response of the comparatoris modeled with the derived ac error. The presented model isuseful for designs using high-speed comparators. In previouswork, the dynamic nature of the comparator that includes thefrequency response of the latch is analyzed [13]. This briefdelivers a frequency model based on the detailed analysis.This brief is organized as follows. Section II shows that thecomparison result depends on the input signal frequency. Theac error voltage is derived by the theoretical analysis with asmall-signal model, and the comparator is modeled to representthe frequency dependence in Section III. Section IV providesSPICE simulation results with a 0.18-m CMOS process modelto confirm the derived model. The conclusion is drawn inSection V.II. EFFECT OF THE INPUT SIGNAL CHANGEFig. 1 shows a schematic of the clocked CMOS comparatorhaving two parts, a preamp and a regenerative latch. The inputsignal is continuously applied to the comparator. The preampdrives the latch according to the voltage difference between vinand vref . When CLK is high, the latch is in a reset state andtracks the difference signal with nonzero ON-resistance of theswitch. At this tracking mode, the comparator shows a negativeexponential response since vout is shorted to ground. Just atthe time of the switch turning to open, vout is regenerativelyamplified to the rail-to-rail level by a positive feedback loopin the amplifier of latch, and finally, the comparison result ofvin and vref is stored in the latch. Since the regeneration timeconstant is a finite nonzero value, the signal generated by thepreamp during regeneration introduces the ac error voltage,which depends on the input signal frequency.Fig. 2 shows the transient simulation results of the clockedcomparator, in which the ac error voltage is described. The1549-7747/$26.00 2010 IEEEOKURA et al.: FREQUENCY MODEL OF A CONTINUOUSLY DRIVEN CLOCKED CMOS COMPARATOR 957Fig. 2. Comparator transient response depending on the input signal fre-quency. (a) Input signal vin. (b) Comparator output vout.input signal is a sine wave whose frequency is 200, 160, 120,and 80 MHz, which is continuously applied to the comparatorinput [see Fig. 2(a)]. The reference signal is a 40-mV dcvoltage. The comparator switches from the tracking mode to theregeneration mode at 50 ns. At this instance, all input signalsare 0 mV, and all tracked signals are negative. As shown inFig. 2(b), the outputs of 200- and 160-MHz cases increase,whereas the outputs of 120- and 80-MHz cases decrease. Thismeans that the comparison result depends on both the differencesignal and the ac error voltage, which becomes larger as thefrequency increases. The ac error voltage is a function of inputsignal frequency because it is introduced by the input signalchanges in a short period just after the clock edge while theregeneration gain is still small.III. SMALL-SIGNAL ANALYSISA. Theoretical DerivationThe ac error voltage is studied with a small-signal circuit onthe transition from the tracking mode to the regeneration mode.For simplicity, the comparator switches from the tracking modeto the regeneration mode at 0.0 s. The comparator is firstanalyzed in the tracking mode to derive the initial value in theregeneration mode. The regeneration process is then analyzed.The ac error voltage is derived from the zero-to-one transitionpoint V0to1, which is the reference voltage when the comparatoris in a metastable state for a given input signal. The comparisonresult is logic high if vref < V0to1, whereas it is logic low ifvref > V0to1. The regeneration response is represented with thepositive exponential term. When the coefficient of the positiveFig. 3. Equivalent circuit of the comparator.exponential term is 0.0, the comparator results in a metastablestate, and V0to1 is derived. The ac error voltage is given byVerr,ac = V0to1 vin(0) (1)where vin(0) is the sampled input signal.The comparator is simplified as the equivalent circuit shownin Fig. 3. The preamp is composed of an amplifier and atransconductance gmin [14]. The amplifier is not broken downinto components since it is conventionally well known. Theswitching conductance is gsw. The negative conductance gmlprovides regenerative feedback of the latch. The variable ,which is the ratio of gsw to gml, is kept above 1.0 so that thelatch can reset the prior data stored. The static dc offset voltageVos,static is in series to the negative conductance because thecomparator has a potentially large offset voltage originatingfrom the latch whose device size is kept small to minimize theregeneration time constant and power consumption. The outputcapacitance is represented as CL. A sinusoidal input signalapplied to the comparator is given byvin(t) = sin(int + in) (2)where in and in are the frequency and the phase, respectively.The input signal amplitude is normalized to 1.0 V. The transferfunction of the amplifier in the preamp Hpreamp(s) is given byHpreamp(s) =Apreamp1 + spreamp(3)where Apreamp and preamp are the dc gain and the timeconstant, respectively. The amplifier output is given by theLaplace transform of (2) and (3) asVx(s)=Apreamp1+spreamp(ssin(in)+in cos(in)s2+2in vrefs). (4)Based on KCL, the latch output during the tracking mode isgiven bysCLVout(s)+gmlVout(s)+(gml)(Vout(s) Vos,statics)= gminVx(s)(t958 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 57, NO. 12, DECEMBER 2010which is presented asvout(0) =Apreampgmin( 1)gml(K1K2 sin(in + 1 + 2) vref gmlApreampgminVos,static)(8)K1 (2in2preamp + 1)1/2 (9)1 arctan(inpreamp) (10)K2 (2in2track + 1)1/2 (11)2 arctan(intrack). (12)The tracking error, which has been analyzed in [7], [10], and[11], is not considered in this analysis, so that the comparator issupposed to be at steady state until 0.0 s.In the regeneration mode, KCL gives the output signalsCLVout(s)+(gml)(Vout(s) Vos,statics)=gminVx(s)+CLvout(0) (t0) (13)Vout(s)=regvout(0)+ gmingml Vx(s)Vos,statics1sreg (14)reg =CLgml(15)where reg is the regeneration time constant [12]. Substituting(4) and (8) into (14), the inverse Laplace transform of theequation gives the output presented asvout(t) = ac1 exp(jint) + ac1 exp(jint)+ ac2 + ac3 exp(treg)(t 0) (16)where the coefficients ac1, ac2, and ac3 are independent oftime (see the Appendix). vout(t) either increases or decreasesexponentially with time depending on the sign of ac3, whereasthe first three terms in the right side of (16) do not contribute tothe regeneration result. If ac3 > 0, vout(t) ends up with logichigh, whereas vout(t) does with logic low if ac3 < 0. Whenac3 = 0, the comparator is in a metastable state. From ac3 = 0,the zero-to-one transition point is represented asV0to1 =K1K2K3 sin(in + 1 + 2 + 3)+gmlApreampgminVos,static (17)K3 (1 + 2in2reg)1/2 (18)3 arctan (inreg) . (19)The first term in the right side of (17) shows the magnitude(K1K2K3) and the phase shift (1 + 2 + 3) for sin(in).The variables K1, 1, K2, 2, K3, and 3, which are givenby (9)(12), (18), and (19), respectively, are the functions ofthe input signal frequency in. The second term in the rightside of (17) indicates the input-referred voltage of the static dcoffset, which does not affect the ac error. The ac error voltageis therefore represented asVerr,ac = K1K2K3 sin(in + 1 + 2 + 3) sin(in) (20)Fig. 4. Frequency model of the comparator. (a) With an additional summingblock. (b) Replacement of (a).referring to (1). It is noted that the sampled input signal is givenby vin(0) = sin(in). The ac error voltage is the attenuatedinput signal with phase shifts.B. Behavioral ModelThe frequency response of the comparator is modeled withthe derived ac error voltage. The comparator is conventionallymodeled as a summing block with quantization noise added tothe input signal [15]. When the ac error is taken into account,the comparator is modeled with an additional summing block,as shown in Fig. 4(a), where the sum of the input signal and theac error is noted as a zero-to-one transition point. From (20),the sum of the sampled input signal and the ac error voltage isgiven byV 0to1(in) = vin(0) + Verr,ac=K(in) sin (in + (in)) (21)K(in) K1 K2 K3 (22)(in) 1 + 2 + 3 (23)noting that the variables Ki and i (i = 1, 2, 3) are functionsof the input signal frequency in. Since the sampled signal issin(in), (21) replaces the model of the comparator shown inFig. 4(a) with that in Fig. 4(b). The transfer function H(s) isgiven by the magnitude K(in) and the phase (in). In orderto derive H(s), magnitude Ki and phase i (i = 1, 2, 3) aretransformed as follows: K1 and 1, which were given by (9)and (10), respectively, are transformed toK1 = 11 + jinpreamp (24)1 =(11 + jinpreamp)(25)K2 and 2, which were given by (11) and (12), respectively, aretransformed toK2 = 11 + jintrack (26)2 =(11 + jintrack)(27)OKURA et al.: FREQUENCY MODEL OF A CONTINUOUSLY DRIVEN CLOCKED CMOS COMPARATOR 959Fig. 5. Plot of (30) when preamp = reg.and K3 and 3, which were given by (18) and (19), respectively,are transformed toK3 = 11 jinreg (28)3 =(11 jinreg). (29)Therefore, H(s) is derived asH(s) =11 + spreamp Hpreamp(s) 11 + strack Htrack(s) 11 sreg Hreg(s). (30)The three poles of (30) correspond to the poles of the preamp,the latch in the tracking mode, and the latch in the regenerationmode, respectively.The plot of (30) is shown in Fig. 5, setting preamp = reg asa simple example. It is noted that track is given by reg/( 1)according to (7) and (15). The bandwidth is saturated when > 2, because the bandwidth is limited by Hpreamp(s) andHreg(s), whose poles are located at a lower frequency than thatof Htrack(s). On the other hand, the phase delay at 3 dBdecreases as increases because the sum of angles ofHpreamp(s) and Hreg(s) is zero and the phase shift dependsonly on Htrack(s). The phase shift in the comparator is keptsmall by setting high at preamp = reg. This is useful for thedesign of the comparator, which is sensitive to the phase shift.IV. SIMULATION RESULTFig. 6 presents an example schematic of a fully differen-tial high-speed comparator. Two differential input pairs (Mn1,Mn2, and Mn3, Mn4) sense the difference between the analoginputs and the reference voltages and generate currents accord-ingly. These currents are mirrored from load transistors (Mp1and Mp2) to p-channel transistors (Mp3 and Mp4). A pair ofp-channel cascode transistors (Mp5 and Mp6) biased at a givenvoltage Vb prevents kickback noise [16]. The latch utilizes anFig. 6. Example of a fully differential high-speed CMOS comparator.TABLE IVARIABLES OF THE COMPARATOR DERIVED FROM SPICE SIMULATIONSFig. 7. Comparison of zero-to-one transition points between the model andsimulated results for input signal frequencies.n-channel cross-coupled transistor (Mn6 and Mn7) and aCMOS switch (Mn5 and Mp7).Table I shows the variables of the comparator derivedfrom SPICE simulations with the transistor-level netlist and a0.18-m CMOS process model. It is noted that the two poles ofthe preamp, namely, the mirror pole and the cascode pole, arerepresented with preamp1 and preamp2.The simulated zero-to-one transition points versus the inputsignal frequency in are shown in Fig. 7, where the input signalphase is 0 rad. The dots are found with transient simulationruns. The solid line shows the presented frequency model of thecomparator, where the variables listed in Table I are used. Thesolid line is close to the dots, so that the presented model pre-cisely estimates the zero-to-one transition points. The dashedline shows the conventional model only with the frequencyresponse of the preamp. The conventional model significantlydeviates from the dots because the effect of the input signalduring regeneration is large at high frequencies.960 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 57, NO. 12, DECEMBER 2010Fig. 8. Comparison of zero-to-one transition points between the model andsimulated results for input signal phases at in = 3.14 Grad/s.Fig. 8 shows the zero-to-one transition points versus the inputsignal phase in at in = 3.14 Grad/s. The ac error voltage isnot negligible at this high frequency. The presented model ofthe solid line shows good fitting to the simulation results of dotsand provides fine estimation of the zero-to-one transition pointsat each input signal phase, whereas the mismatch betweenthe conventional model and simulation results is considerablylarge. These simulation results demonstrate the accuracy of thepresented model.V. CONCLUSIONA novel frequency model of a continuously driven clockedcomparator has been presented. The model includes a transferfunction to represent the effect of the input signal during regen-eration, which was derived from the small-signal analysis onthe transition from the tracking mode to the regeneration mode.The transfer function is given by the product of three poles,which are functions of basic design parameters. In addition, acomparison between the model estimation and simulated resultsfor an example design has been described. The presented modelshows a precise estimation of a comparator response withhigh-frequency input signals. Therefore, the presented modelprovides a valuable insight for high-speed comparator design.APPENDIXThe time response of the comparator during the regenerationmode is given by (16) with coefficients ac1, ac2, and ac3. Thesecoefficients are respectively given byac1 = ApreampK1 gmingmlsin(in + 1) + j cos(in + 1)2(1 + jinreg),(31)ac2 =Apreampgmingmlvref + Vos,static (32)ac3 =Apreampgmingml(K1K3 sin(in + 1 + 3) vref) Vos,static + vout(0). (33)The first two terms in the right side of (16) is representedwith (31) asac1 exp(jint) + ac1 exp(jint)= ApreampK1K3 gmingmlsin(int + in + 1 + 3). (34)ACKNOWLEDGMENTS. Okura would like to thank T. Wakimoto and C. W.Mangelsdorf of Analog Devices, K. K., for making possible theinternship during which this work was performed and for theirassistance, support, and encouragement throughout this project.This work was partly carried out at the Frontier Research Basefor Global Young Researchers, Osaka University, on the Pro-gram of Promotion of Environmental Improvement to EnhanceYoung Researchers Independence, the Special CoordinationFunds for Promoting Science and Technology, Japan Ministryof Education, Culture, Sports, Science and Technology.REFERENCES[1] H. J. M. Veendric, The behavior of flip-flops used as synchronizers andprediction of their failure rate, IEEE J. Solid-State Circuits, vol. SSC-15,no. 2, pp. 169176, Apr. 1980.[2] R. Sarpeshkar, J. L. Wyatt, Jr., N. C. Lu, and P. D. Gerber, Mismatchsensitivity of a simultaneously latched CMOS sense amplifier, IEEE J.Solid-State Circuits, vol. 26, no. 10, pp. 14131422, Oct. 1991.[3] W. A. M. Van Noije, W. T. Liu, and S. J. Navarro, Jr., Precise finalstate determination of mismatched CMOS latches, IEEE J. Solid-StateCircuits, vol. 30, no. 5, pp. 607611, May 1995.[4] G. M. Yin, F. O. Eynde, and W. Sansen, A high-speed CMOS comparatorwith 8-b resolution, IEEE J. Solid-State Circuits, vol. 27, no. 2, pp. 208211, Feb. 1992.[5] B. Zojer, R. Petschacher, and W. A. Luschnig, A 6-bit/200-MHz fullNyquist A/D converter, IEEE J. Solid-State Circuits, vol. SSC-20, no. 3,pp. 780786, Jun. 1985.[6] B. Peetz, B. D. Hamilton, and J. Kang, An 8-bit 250 Megasample persecond analog-to-digital converter: Operation without a sample and hold,IEEE J. Solid-State Circuits, vol. SSC-21, no. 6, pp. 9971002, Dec. 1986.[7] R. J. V. D. Plassche and P. Baltus, An 8-bit 100-MHz full-Nyquist analog-to-digital converter, IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 13341344, Dec. 1988.[8] C. W. Mangelsdorf, A 400-MHz input Flash converter with errorcorrection, IEEE J. Solid-State Circuits, vol. 25, no. 1, pp. 184191,Feb. 1990.[9] I. Mehr and D. Dalton, A 500-MSample/s, 6-bit Nyquist-rate ADCfor disk-drive read-channel applications, IEEE J. Solid-State Circuits,vol. 34, no. 7, pp. 912920, Jul. 1999.[10] M. Choi and A. A. Abidi, A 6-b 1.3-Gsample/s A/D converter in0.35-m CMOS, IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 18471858, Dec. 2001.[11] K. Uyttenhove, J. Vandenbussche, E. Lauwers, G. Gielen, andM. Steyaert, Design techniques and implementation of an 8-bit 200-MS/sinterpolating/averaging CMOS A/D converter, IEEE J. Solid-StateCircuits, vol. 38, no. 3, pp. 483494, Mar. 2003.[12] B. Razavi and B. A. Wooley, Design techniques for high-speed, high-resolution comparators, IEEE J. Solid-State Circuits, vol. 27, no. 12,pp. 19161926, Dec. 1992.[13] S. Okura, T. Ohkura, K. Taniguchi, and H. Shibata, Frequency responseanalysis of latch utilized in high-speed comparator, in Proc. IEEE Int.Conf. Electron., Circuits, Syst., 2006, pp. 10771080.[14] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout,and Simulation. New York: Wiley-IEEE Press, 1997.[15] R. J. Baker, CMOS, Mixed-Signal Circuit Design. New York: Wiley-IEEE Press, 2002.[16] K. Sushihara, H. Kimura, Y. Okamoto, K. Nishimura, and A. Matsuzawa,A 6b 800 MSample/s CMOS A/D converter, in Proc. Int. Solid StateCircuits Conf., Feb. 2000, pp. 428429. /ColorImageDict > /JPEG2000ColorACSImageDict > /JPEG2000ColorImageDict > /AntiAliasGrayImages false /CropGrayImages true /GrayImageMinResolution 300 /GrayImageMinResolutionPolicy /OK /DownsampleGrayImages true /GrayImageDownsampleType /Bicubic /GrayImageResolution 300 /GrayImageDepth -1 /GrayImageMinDownsampleDepth 2 /GrayImageDownsampleThreshold 1.50000 /EncodeGrayImages true /GrayImageFilter /DCTEncode /AutoFilterGrayImages false /GrayImageAutoFilterStrategy /JPEG /GrayACSImageDict > /GrayImageDict > /JPEG2000GrayACSImageDict > /JPEG2000GrayImageDict > /AntiAliasMonoImages false /CropMonoImages true /MonoImageMinResolution 1200 /MonoImageMinResolutionPolicy /OK /DownsampleMonoImages true /MonoImageDownsampleType /Bicubic /MonoImageResolution 600 /MonoImageDepth -1 /MonoImageDownsampleThreshold 1.50000 /EncodeMonoImages true /MonoImageFilter /CCITTFaxEncode /MonoImageDict > /AllowPSXObjects false /CheckCompliance [ /None ] /PDFX1aCheck false /PDFX3Check false /PDFXCompliantPDFOnly false /PDFXNoTrimBoxError true /PDFXTrimBoxToMediaBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXSetBleedBoxToMediaBox true /PDFXBleedBoxToTrimBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXOutputIntentProfile (None) /PDFXOutputConditionIdentifier () /PDFXOutputCondition () /PDFXRegistryName () /PDFXTrapped /False /Description > /Namespace [ (Adobe) (Common) (1.0) ] /OtherNamespaces [ > /FormElements false /GenerateStructure false /IncludeBookmarks false /IncludeHyperlinks false /IncludeInteractive false /IncludeLayers false /IncludeProfiles false /MultimediaHandling /UseObjectSettings /Namespace [ (Adobe) (CreativeSuite) (2.0) ] /PDFXOutputIntentProfileSelector /DocumentCMYK /PreserveEditing true /UntaggedCMYKHandling /LeaveUntagged /UntaggedRGBHandling /UseDocumentProfile /UseDocumentBleed false >> ]>> setdistillerparams> setpagedevice