OKURA et al.: FREQUENCY MODEL OF A CONTINUOUSLY DRIVEN CLOCKED CMOS COMPARATOR 957
Fig. 2. Comparator transient response depending on the input signal fre-
quency. (a) Input signal vin. (b) Comparator output vout.
input signal is a sine wave whose frequency is 200, 160, 120,
and 80 MHz, which is continuously applied to the comparator
input [see Fig. 2(a)]. The reference signal is a 40-mV dc
voltage. The comparator switches from the tracking mode to the
regeneration mode at 50 ns. At this instance, all input signals
are 0 mV, and all tracked signals are negative. As shown in
Fig. 2(b), the outputs of 200- and 160-MHz cases increase,
whereas the outputs of 120- and 80-MHz cases decrease. This
means that the comparison result depends on both the difference
signal and the ac error voltage, which becomes larger as the
frequency increases. The ac error voltage is a function of input
signal frequency because it is introduced by the input signal
changes in a short period just after the clock edge while the
regeneration gain is still small.
III. SMALL-SIGNAL ANALYSIS
A. Theoretical Derivation
The ac error voltage is studied with a small-signal circuit on
the transition from the tracking mode to the regeneration mode.
For simplicity, the comparator switches from the tracking mode
to the regeneration mode at 0.0 s. The comparator is first
analyzed in the tracking mode to derive the initial value in the
regeneration mode. The regeneration process is then analyzed.
The ac error voltage is derived from the zero-to-one transition
point V0to1, which is the reference voltage when the comparator
is in a metastable state for a given input signal. The comparison
result is logic high if vref < V0to1, whereas it is logic low if
vref > V0to1. The regeneration response is represented with the
positive exponential term. When the coefficient of the positive
Fig. 3. Equivalent circuit of the comparator.
exponential term is 0.0, the comparator results in a metastable
state, and V0to1 is derived. The ac error voltage is given by
Verr,ac = V0to1 − vin(0) (1)
where vin(0) is the sampled input signal.
The comparator is simplified as the equivalent circuit shown
in Fig. 3. The preamp is composed of an amplifier and a
transconductance gmin . The amplifier is not broken down
into components since it is conventionally well known. The
switching conductance is gsw. The negative conductance −gml
provides regenerative feedback of the latch. The variable γ,
which is the ratio of gsw to gml, is kept above 1.0 so that the
latch can reset the prior data stored. The static dc offset voltage
Vos,static is in series to the negative conductance because the
comparator has a potentially large offset voltage originating
from the latch whose device size is kept small to minimize the
regeneration time constant and power consumption. The output
capacitance is represented as CL. A sinusoidal input signal
applied to the comparator is given by
vin(t) = sin(ωint + θin) (2)
where ωin and θin are the frequency and the phase, respectively.
The input signal amplitude is normalized to 1.0 V. The transfer
function of the amplifier in the preamp Hpreamp(s) is given by
1 + sτpreamp
where Apreamp and τpreamp are the dc gain and the time
constant, respectively. The amplifier output is given by the
Laplace transform of (2) and (3) as
Based on KCL, the latch output during the tracking mode is
958 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 12, DECEMBER 2010
which is presented as
(γ − 1)gml
K1K2 sin(θin + θ1 + θ2)
− vref − gml
preamp + 1
θ1 ≡ −arctan(ωinτpreamp) (10)
track + 1
θ2 ≡ −arctan(ωinτtrack). (12)
The tracking error, which has been analyzed in , , and
, is not considered in this analysis, so that the comparator is
supposed to be at steady state until 0.0 s.
In the regeneration mode, KCL gives the output signal
=gminVx(s)+CLvout(0−) (t≥0) (13)
τregvout(0−)+ gmingml Vx(s)−
where τreg is the regeneration time constant . Substituting
(4) and (8) into (14), the inverse Laplace transform of the
equation gives the output presented as
vout(t) = ac1 · exp(−jωint) + ac1 · exp(jωint)
+ ac2 + ac3 · exp
(t ≥ 0) (16)
where the coefficients ac1, ac2, and ac3 are independent of
time (see the Appendix). vout(t) either increases or decreases
exponentially with time depending on the sign of ac3, whereas
the first three terms in the right side of (16) do not contribute to
the regeneration result. If ac3 > 0, vout(t) ends up with logic
high, whereas vout(t) does with logic low if ac3 < 0. When
ac3 = 0, the comparator is in a metastable state. From ac3 = 0,
the zero-to-one transition point is represented as
V0to1 =K1K2K3 sin(θin + θ1 + θ2 + θ3)
1 + ω2inτ
θ3 ≡ arctan (ωinτreg) . (19)
The first term in the right side of (17) shows the magnitude
(K1K2K3) and the phase shift (θ1 + θ2 + θ3) for sin(θin).
The variables K1, θ1, K2, θ2, K3, and θ3, which are given
by (9)–(12), (18), and (19), respectively, are the functions of
the input signal frequency ωin. The second term in the right
side of (17) indicates the input-referred voltage of the static dc
offset, which does not affect the ac error. The ac error voltage
is therefore represented as
Verr,ac = K1K2K3 sin(θin + θ1 + θ2 + θ3)− sin(θin) (20)
Fig. 4. Frequency model of the comparator. (a) With an additional summing
block. (b) Replacement of (a).
referring to (1). It is noted that the sampled input signal is given
by vin(0) = sin(θin). The ac error voltage is the attenuated
input signal with phase shifts.
B. Behavioral Model
The frequency response of the comparator is modeled with
the derived ac error voltage. The comparator is conventionally
modeled as a summing block with quantization noise added to
the input signal . When the ac error is taken into account,
the comparator is modeled with an additional summing block,
as shown in Fig. 4(a), where the sum of the input signal and the
ac error is noted as a zero-to-one transition point. From (20),
the sum of the sampled input signal and the ac error voltage is
V ′0to1(ωin) = vin(0) + Verr,ac
=K(ωin) sin (θin + θ(ωin)) (21)
K(ωin) ≡K1 ·K2 ·K3 (22)
θ(ωin) ≡ θ1 + θ2 + θ3 (23)
noting that the variables Ki and θi (i = 1, 2, 3) are functions
of the input signal frequency ωin. Since the sampled signal is
sin(θin), (21) replaces the model of the comparator shown in
Fig. 4(a) with that in Fig. 4(b). The transfer function H(s) is
given by the magnitude K(ωin) and the phase θ(ωin). In order
to derive H(s), magnitude Ki and phase θi (i = 1, 2, 3) are
transformed as follows: K1 and θ1, which were given by (9)
and (10), respectively, are transformed to
∣∣∣∣ 11 + jωinτpreamp
1 + jωinτpreamp
K2 and θ2, which were given by (11) and (12), respectively, are
∣∣∣∣ 11 + jωinτtrack
1 + jωinτtrack
OKURA et al.: FREQUENCY MODEL OF A CONTINUOUSLY DRIVEN CLOCKED CMOS COMPARATOR 959
Fig. 5. Plot of (30) when τpreamp = τreg.
and K3 and θ3, which were given by (18) and (19), respectively,
are transformed to
∣∣∣∣ 11− jωinτreg
Therefore, H(s) is derived as
1 + sτpreamp︸ ︷︷ ︸
1 + sτtrack︸ ︷︷ ︸
1− sτreg︸ ︷︷ ︸
The three poles of (30) correspond to the poles of the preamp,
the latch in the tracking mode, and the latch in the regeneration
The plot of (30) is shown in Fig. 5, setting τpreamp = τreg as
a simple example. It is noted that τtrack is given by τreg/(γ − 1)
according to (7) and (15). The bandwidth is saturated when
γ > 2, because the bandwidth is limited by Hpreamp(s) and
Hreg(s), whose poles are located at a lower frequency than that
of Htrack(s). On the other hand, the phase delay at −3 dB
decreases as γ increases because the sum of angles of
Hpreamp(s) and Hreg(s) is zero and the phase shift depends
only on Htrack(s). The phase shift in the comparator is kept
small by setting γ high at τpreamp = τreg. This is useful for the
design of the comparator, which is sensitive to the phase shift.
IV. SIMULATION RESULT
Fig. 6 presents an example schematic of a fully differen-
tial high-speed comparator. Two differential input pairs (Mn1,
Mn2, and Mn3, Mn4) sense the difference between the analog
inputs and the reference voltages and generate currents accord-
ingly. These currents are mirrored from load transistors (Mp1
and Mp2) to p-channel transistors (Mp3 and Mp4). A pair of
p-channel cascode transistors (Mp5 and Mp6) biased at a given
voltage Vb prevents kickback noise . The latch utilizes an
Fig. 6. Example of a fully differential high-speed CMOS comparator.
VARIABLES OF THE COMPARATOR DERIVED FROM SPICE SIMULATIONS
Fig. 7. Comparison of zero-to-one transition points between the model and
simulated results for input signal frequencies.
n-channel cross-coupled transistor (Mn6 and Mn7) and a
CMOS switch (Mn5 and Mp7).
Table I shows the variables of the comparator derived
from SPICE simulations with the transistor-level netlist and a
0.18-μm CMOS process model. It is noted that the two poles of
the preamp, namely, the mirror pole and the cascode pole, are
represented with τpreamp1 and τpreamp2.
The simulated zero-to-one transition points versus the input
signal frequency ωin are shown in Fig. 7, where the input signal
phase is 0 rad. The dots are found with transient simulation
runs. The solid line shows the presented frequency model of the
comparator, where the variables listed in Table I are used. The
solid line is close to the dots, so that the presented model pre-
cisely estimates the zero-to-one transition points. The dashed
line shows the conventional model only with the frequency
response of the preamp. The conventional model significantly
deviates from the dots because the effect of the input signal
during regeneration is large at high frequencies.
960 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 12, DECEMBER 2010
Fig. 8. Comparison of zero-to-one transition points between the model and
simulated results for input signal phases at ωin = 3.14 Grad/s.
Fig. 8 shows the zero-to-one transition points versus the input
signal phase θin at ωin = 3.14 Grad/s. The ac error voltage is
not negligible at this high frequency. The presented model of
the solid line shows good fitting to the simulation results of dots
and provides fine estimation of the zero-to-one transition points
at each input signal phase, whereas the mismatch between
the conventional model and simulation results is considerably
large. These simulation results demonstrate the accuracy of the
A novel frequency model of a continuously driven clocked
comparator has been presented. The model includes a transfer
function to represent the effect of the input signal during regen-
eration, which was derived from the small-signal analysis on
the transition from the tracking mode to the regeneration mode.
The transfer function is given by the product of three poles,
which are functions of basic design parameters. In addition, a
comparison between the model estimation and simulated results
for an example design has been described. The presented model
shows a precise estimation of a comparator response with
high-frequency input signals. Therefore, the presented model
provides a valuable insight for high-speed comparator design.
The time response of the comparator during the regeneration
mode is given by (16) with coefficients ac1, ac2, and ac3. These
coefficients are respectively given by
ac1 = −ApreampK1 gmin
sin(θin + θ1) + j cos(θin + θ1)
2(1 + jωinτreg)
vref + Vos,static (32)
(K1K3 sin(θin + θ1 + θ3)− vref)
− Vos,static + vout(0−). (33)
The first two terms in the right side of (16) is represented
with (31) as
ac1 · exp(−jωint) + ac1 · exp(jωint)
= −ApreampK1K3 gmin
sin(ωint + θin + θ1 + θ3). (34)
S. Okura would like to thank T. Wakimoto and C. W.
Mangelsdorf of Analog Devices, K. K., for making possible the
internship during which this work was performed and for their
assistance, support, and encouragement throughout this project.
This work was partly carried out at the Frontier Research Base
for Global Young Researchers, Osaka University, on the Pro-
gram of Promotion of Environmental Improvement to Enhance
Young Researchers’ Independence, the Special Coordination
Funds for Promoting Science and Technology, Japan Ministry
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