PLL (Tsmc 0.18 process)

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    07-Dec-2014

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Class presentation

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1. EE486 Digital VLSI- Final Project Clock Multiplying DPLL Chen Zhai Klipsch School of Electrical and Computer Engineering New Mexico State University [email_address] 2. Presentation Outline Block Diagram Specification Loop Filter Parameters Sub-blocks Simulation Comments and Questions 3. Block Diagram 4. Specification TSMC 0.18 Standard CMOS Supply Voltage 1.8V Input Frequency 150MHz Output Frequency 750MHz Load 1pF Lock Time ~ micro seconds 5. Loop Filter Spec: Input Frequency Natural Frequency (~Bandwidth) Damping Factor Results: Design Values: R, C1, C2, Ipump Performance: Lock time, etc 6. LinearizedCurrent-StarvedVCOwith Output Buffers 7. LinearizedCurrent-StarvedVCOTuning Curve Vin_max=1.8V Vin_min=Vtn=0.5V Fmax=1.068GHz Fmin=83.26MHz Kvco=758MHz/V 8. Divide by 5 Circuit Sequence: 000 001 0 1 0 0 1 1 100 Synchronous Reset 9. High-speed Phase Frequency Detector 10. Charge-pump 11. DPLL Schematic 12. DPLL Test-bench 13. Simulation Result 14. Simulation Result 15. Simulation Result 16. Simulation Result-Locked 17. Measurement Result Key Parameters of DPLL: Natural Frequency (Bandwidth) Matching (delay, current of charge-pump) Speed (Divide-by-5) Output Frequency 750.00MHz Jitter 10.2ps Lock time ~0.5 us

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